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data sheet no.pd60267 reva typical connection product summary v offset 600 v max. i o +/- 130 ma/270 ma v out 10 v - 20 v t on/off (typ.) 680 ns/150 ns deadtime (typ.) 520 ns half-bridge driver features ? floating channel designed for bootstrap operation ? fully operational to +600 v ? tolerant to negative transient voltage, dv/dt immune ? gate drive supply range from 10 v to 20 v ? undervoltage lockout ? 3.3 v, 5 v, and 15 v input logic compatible ? cross-conduction prevention logic ? internally set deadtime ? high side output in phase with input ? shut down input turns off both channels ? matched propagation delay for both channels description the irs2104 is a high voltage, high speed power mosfet and igbt driver with dependent high and low side referenced output channels. pro prietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. the logic input is compatible with standard cmos or lsttl output, down to 3.3 v logic. the output drivers feature a high pulse current buffer stage designed for minimum driver cross- conduction. the floating channel can be used to drive an n-channel power mosfet or igbt in the high side configuration which operates from 10 v to 600 v. www.irf.com 1 irs2104(s)pbf v cc v b v s ho lo com in sd sd in up to 600 v to load v cc (refer to lead assignment for correct pin configuration). this diagram shows electrical connections only. please refer to our application notes and designtips for proper circuit board layout. preliminary packages 8 lead pdip irs2104 8 lead soic irs2104s
preliminary irs2104(s) pbf www.irf.com 2 symbol definition min. max. units v b high side floating absolute voltage -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side and logic fixed supply voltage -0.3 25 v lo low side output voltage -0.3 v cc + 0.3 v in logic input voltage (in & sd ) -0.3 v cc + 0.3 dv s /dt allowable offset supply voltage transient ? 50 v/ns p d package power dissipation @ t a +25 c (8 lead pdip) ? 1.0 (8 lead soi c) ? 0.625 rth ja thermal resistance, junction to ambient (8 lead pdip) ? 125 (8 lead soic) ? 200 t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage note 1 600 v ho high side floating output voltage v s v b v cc low side and logic fixed supply voltage 10 20 v lo low side output voltage 0 v cc v in logic input voltage (in & sd )0v cc t a ambient temperature -40 125 note 1: logic operational for v s of -5 v to +600 v. logic state held for v s of -5 v to -v bs . (please refer to the design tip dt97-3 for more details). recommended operating conditions the input/output logic timing diagram is shown in fig. 1. for proper operation the device should be used within the recommended conditions. the v s offset rating is tested with all supplies biased at a 15 v differential. c v v w c/w c
irs2104(s) pbf preliminary www.irf.com 3 symbol definition min. typ. max. units t est conditions v ih logic ?1? (ho) & logic ?0? (lo) input voltage 2.5 ? ? v il logic ?0? (ho) & logic ?1? (lo) input voltage ? ? 0.8 v sd,th+ sd input positive going threshold 2.5 ? ? v sd,th- sd input negative going threshold ? ? 0.8 v oh high level output voltage, v bias - v o ? 0.05 0.2 v ol low level output voltage, v o ? 0.02 0.1 i lk offset supply leakage current ? ? 50 v b = v s = 600 v i qbs quiescent v bs supply current ? 30 55 i qcc quiescent v cc supply current ? 150 270 i in+ logic ?1? input bias current ? 3 10 v in = 5 v i in- logic ?0? input bias current ? ? 1 v in = 0 v v ccuv+ v cc supply undervoltage positive going 8 8.9 9.8 threshold v ccuv- v cc supply undervoltage negative going 7.4 8.2 9 threshold i o+ output high short circuit pulsed current 130 290 ? v o = 0 v pw 10 s i o- output low short circuit pulsed current 270 600 ? v o = 15 v pw 10 s symbol definition min. typ. max. units t est conditions t on turn-on propagation delay ? 680 820 v s = 0 v t off turn-off propagation delay ? 150 220 v s = 600 v t sd shutdown propagation delay ? 160 220 t r turn-on rise time ? 70 170 t f turn-off fall time ? 35 90 dt deadtime, ls turn-off to hs turn-on & 400 520 650 hs turn-on to ls turn-off static electrical characteristics v bias (v cc , v bs ) = 15 v and t a = 25 c unless otherwise specified. the v in , v th, and i in parameters are referenced to com. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. dynamic electrical characteristics v bias (v cc , v bs ) = 15 v, c l = 1000 pf and t a = 25 c unless otherwise specified. v v ma mt delay matching, hs & ls turn-on/off ? ? 60 ns a v cc = 10 v to 20 v i o = 2 ma v in = 0 v or 5 v
preliminary irs2104(s) pbf www.irf.com 4 functional block diagram lead definitions symbol description in logic input for high and low side gate driver outputs (ho and lo), in phase with ho logic input for shutdown v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side and logic fixed supply lo low side gate drive output com low side return sd lead assignments 8 lead pdip 8 lead soic IRS2104PBF irs2104spbf 1 2 3 4 8 7 6 5 v cc in sd com v b ho v s lo 1 2 3 4 8 7 6 5 v cc in sd com v b ho v s lo vb ho vs in sd dead time & shoot-through prevention pulse gen pulse filter hv level shift r s q vcc lo com uv detect
irs2104(s) pbf preliminary www.irf.com 5 figure 5. delay matching waveform definitions ho 50% 50% 10% lo 90% mt ho lo mt in (lo) in (ho) figure 4. deadtime waveform definitions in ho 50% 50% 90% 10% lo 90% 10% dt dt figure 3. shut down w aveform definitions sd t sd ho lo 50% 90% figure 1. input/output timing diagram sd in ho lo figure 2. switching time waveform definitions in (ho) t r t on t f t off lo ho 50% 50% 90% 90% 10% 10% in (lo)
preliminary irs2104(s) pbf www.irf.com 6 figure 6a. turn-on time vs. temperature figure 6b. turn-on time vs. supply voltage figure 7a. turn-off time vs. temperature figure 7b. turn-off time vs. supply voltage temperature (c) vbias supply voltage (v) temperature (c) vbias supply voltage (v) turn-off delay time (ns) 0 100 200 300 400 500 10 12 14 16 18 20 max . ty p. turn-off delay time (ns) 0 200 400 600 800 1000 1200 1400 -50 -25 0 25 50 75 100 125 turn-on delay time (ns) ma x. typ. turn-on delay time (ns) 0 200 400 600 800 1000 1200 1400 10 12 14 16 18 20 y() ma x . ty p. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max . ty p. 0 200 400 600 800 1000 0 2 4 6 8 101214161820 turn-on delay time (ns ) max . typ . 0 200 400 600 800 1000 0 2 4 6 8 101214161820 turn-off delay time (ns max . typ figure 7c. turn-off time vs. input voltage figure 6c. turn-on time vs. input voltage input voltage (v) input voltage (v)
irs2104(s) pbf preliminary www.irf.com 7 figure 8a. shutdown time vs. temperature figure 8b. shutdown time vs. voltage vbias supply voltage (v) temperature (c) shutdown delay time (ns) 0 100 200 300 400 500 10 12 14 16 18 20 max . ty p. shutdown delay time (ns) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 typ. m ax. figure 10a. turn-off fall time vs. temperature temperature (c) figure 10b. turn-off fall time vs. input voltage turn-off fall time (ns) turn-off fall time (ns) figure 9a. turn-on rise time vs. temperature figure 9b. turn-on rise time vs. voltage temperature (c) vbias supply voltage (v) turn-on rise time (ns) turn-on rise time (ns) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max max. typ. 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) ( max. typ. 0 50 100 150 200 -50 -25 0 25 50 75 100 125 max. typ. 0 50 100 150 200 10 12 14 16 18 20 input voltage max. typ.
preliminary irs2104(s) pbf www.irf.com 8 0 1 2 3 4 5 6 7 8 10 12 14 16 18 20 v bais supply voltage (v) 0 1 2 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 figure 13a. logic "0" (ho) & logic ?1? (lo) & active sd input voltage vs. temperature temperature (c) vcc supply voltage (v) figure 13b. logic "0" (ho) & logic ?1? (lo) & active sd input voltage vs. voltage 0 0.8 1.6 2.4 3.2 4 10 12 14 16 18 20 input voltage (v) max . 0 0.8 1.6 2.4 3.2 4 -50-250 255075100125 input voltage (v) ma x . temperature (c) vbias supply voltage (v) deadtime (ns) figure 11a. deadtime vs. temperature deadtime (ns) figure 11b. deadtime vs. voltage 0 200 400 600 800 1000 1200 1400 -50 -25 0 25 50 75 100 125 max. typ. mi n. 0 200 400 600 800 1000 1200 1400 10 12 14 16 18 20 m ax. typ. mi n. temperature ( o c) input voltage (v) input voltage (v) figure12a. logic "1" input voltage vs. temperature figure 12b. logic "1" input voltage vs. supply voltage min. min min. min.
irs2104(s) pbf preliminary www.irf.com 9 offset supply leakage current ( figure 16a. offset supply current vs. temperature offset supply leakage current ( figure 16b. offset supply current vs. voltage 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max . 0 100 200 300 400 500 0 100 200 300 400 500 600 max . vb boost voltage (v) figure 14a. high level output voltage vs. temperature figure 14b. high level output voltage vs. supply voltage high level output voltage (v) high level output voltage (v) v bias supply voltage (v) 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) 0.0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 figure 15a. low level output voltage vs. temperature figure 15b. low level output voltage vs. supply voltage low level output voltage (v) low level output voltage (v) 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) 0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v bias supply voltage (v) max. typ. max. typ. max. typ. max. typ.
preliminary irs2104(s) pbf www.irf.com 10 figure 18a. vcc supply current vs. temperature vcc supply current ( a) vcc supply current ( a) figure 18b. vcc supply current vs. voltage vcc supply voltage (v) figure 19a. logic"1" input current vs. temperature temperature (c) logic 1? input current ( a) logic 1? input current ( a) figure 19b. logic"1" input current vs. voltage 0 100 200 300 400 500 600 700 10 12 14 16 18 20 ma x . ty p. 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 max . ty p. 0 5 10 15 20 25 30 10 12 14 16 18 20 max . ty p. vcc supply voltage (v) 0 100 200 300 400 500 600 700 -50-250 255075100125 ma x . typ. temperature (c) figure 17a. v bs supply current vs. temperature figure 17b. v bs supply current vs. voltage vbs floating supply voltage (v) temperature (c) vbs supply current ( a) vbs supply current ( a) 0 30 60 90 120 150 10 12 14 16 18 20 max . ty p. 0 30 60 90 120 150 -50 -25 0 25 50 75 100 125 max . ty p.
irs2104(s) pbf preliminary www.irf.com 11 0 100 200 300 400 500 -50-25 0 25 50 75100125 logic ?0? input current ( a) figure 20a. logic "0" input current vs. temperature temperature (c) vcc supply voltage (v) figure 20b. logic "0" input current vs. voltage 0 1 2 3 4 5 10 12 14 16 18 20 logic "0" input current (ua) max . 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 ma x . vcc uvlo threshold +(v) figure 21a. vcc undervoltage threshold(+) vs. temperature temperature (c) figure 21b. vcc undervoltage threshold(-) vs. temperature vcc uvlo threshold - (v) output source current (ma) figure 22a. output source current vs. temperature temperature (c) figure 22b. output source current vs. voltage output source current (ma) 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 ma x . min . ty p. 6 7 8 9 10 11 -50-25 0 25 50 75100125 max . min. ty p. temperature (c) vbias supply voltage (v) typ. min. 0 100 200 300 400 500 10 12 14 16 18 20 min . ty p.
preliminary irs2104(s) pbf www.irf.com 12 output sink current (ma) temperature (c) figure 23a. output sink current vs. temperature figure 23b. output sink current vs. supply voltage output sink current (ma) vbias supply voltage (v) figure 24a. sd input positive going threshold (+) vs. temperature figure 24b. sd input positive going threshold (+) vs. supply voltage temperature (c) v cc supply voltage (v) 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 sd input threshold (+) (v) 1 2 3 4 5 6 10 12 14 16 18 20 sd input threshold (+) (v) max. max. 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 0 200 400 600 800 1000 10 12 14 16 18 20 min. typ. min. typ.
irs2104(s) pbf preliminary www.irf.com 13 01-6014 01-3003 01 (ms-001ab) 8 lead pdip 01-6027 01-0021 11 (ms-012aa) 8 lead soic 87 5 65 d b e a e 6x h 0.25 [.010] a 6 4 3 12 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & tolerancing per asme y14.5m-1994. 2. controlling dimension: millimeter 3. dimensions are shown in millimeters [inches]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions not to exceed 0.25 [.010]. 7 dimension is the length of lead for soldering to a substrate. mold protrusions not to exceed 0.15 [.006]. 0.25 [.010] cab e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 basic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters inches min max dim 8 e c .0075 .0098 0.19 0.25 .025 basic 0.635 basic case outline
preliminary irs2104(s) pbf www.irf.com 14 carrier tape dimension for 8soicn code min max min max a 7 .9 0 8.1 0 0.31 1 0 .3 18 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5 .4 5 5.5 5 0.21 4 0 .2 18 e 6 .3 0 6.5 0 0.24 8 0 .2 55 f 5 .1 0 5.3 0 0.20 0 0 .2 08 g 1.5 0 n/a 0.059 n/a h 1 .5 0 1.6 0 0.05 9 0 .0 62 m etr ic im p erial reel d im ension s for 8soic n code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1 .9 5 2.4 5 0.76 7 0 .0 96 e 98.00 102.00 3.858 4.015 f n /a 1 8. 40 n /a 0 .7 24 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 m etr ic im p erial e f a c d g a b h n ote : co ntrolling d imension in mm load ed ta pe feed direction a h f e g d b c tape & reel 8-lead soic
irs2104(s) pbf preliminary www.irf.com 15 order information 8-lead pdip IRS2104PBF 8-lead soic irs2104spbf 8-lead soic tape & reel irs2104strpbf ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 this product has been qualified per industrial level data and specifications subject to change without notice. 5/11/2006 leadfree part marking information lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code s

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